Frequency tolerance and stability : Deviation from the nominal frequency. Typically, an oscillator will have a specified frequency around which the instabilities of the device are centered. The frequency tolerance (sometimes referred to as calibration) of the oscillator is the potential margin of error at an ambient temperature of 25° C under normal voltage and load. The frequency stability is the measurable accuracy associated with changes in operating temperature, supply voltage, loading changes and ageing.
Operating temperature range : Temperature range within which output frequencies and other output signal characteristics meet the specifications.
Frequency vs power source variation charcteristics : Rate of output frequency change given when only power source voltage is changed, with the other conditions unchanged.
Logic "0" / Logic "1" : In digital logic, signal parameters are referenced in term of one or two states. The states are measured as voltage levels with some higher potential being the logic "1" and some lower potential being the logic "0". The actual voltage values vary with the type of logic required. For example, with TTL applications, logic "0" is considered to be 0.4 V max. and logic "1" is considered to be 2.4 V max., whereas ECL operations, supplied with a negative voltage, produce an logic "0" at -1.8V and a logic "1" at -1 V.
Duty cycle : The following formula is used to calculate the value that represents the duty cycle of the waveform:
High Time (in Sec.) /period (in Sec.) = duty cycle (%): The period is the amount of time it takes the waveform to complete one cycle. During this cycle, the waveform is moving toward, is at, or moving away from a logic "1" state for a certain percentage of the total period. This percentage is referred to as the duty cycle, and must be measured at some threshold voltage value, contingent on the type of logic. The duty cycle is always given with two value referenced (i.e. 45/55 %)
Rise / Fall time : The output of an oscillator alternates between "0" and "1" logic states. As can be seen from the waveform in the following figure, it takes the oscillator a period of time to transcend from the "0" state to the "1" state. This transition state is referred as the rise time. Conversely, the fall time is the amount of time it takes for the time it takes for the waveform to go from 20% to 80% of its peak to peak value. In other words, for a 5 V peak to peak waveform, the rise/fall time values will be measured between 1 V and 4 V. These threshold values differ between logic types.
TTL " Compatible" : Lower power and faster CMOS technology has surpassed bipolar TTL technology. SOOJUNG offers a line of "dual compatible" oscillators which are essentially HCMOS, tested to TTL parameters. Since an HCMOS waveform typically swings from rail to rail (0V to 5V) and the required levels for TTL logic are 0.4 V to 2.4V, HCMOS ha no problem driving several or more TTL loads.
Output type levels : Output can be specified as either sine wave or logic (TTL, CMOS, ECL, ...). Associated parameters include levels, load impedance and stability, source impedance, harmonic and spur levels and the frequency sensitivity to load changes. In the case of logic signals, the number of gates, duty cycle, rise and fall time are specified. When absolute best phase noise is required, sine wave signals are preferred, as most logic type have higher phase noise floors.
standard output are as follows
|TTL :||VOL = 0.4 maximum|| |
|(VCC-1.06) VOH (VCC-0.65)|
|VOH = 2.4 minimum||(VCC-1.95) VOL (VCC-1.57)|
|HCMOS :||VOL=10% maximum||
|(VCC-1.95) VOL (VCC-1.57)|
|VOH=90% minimum||-1.06 VOH -0.65|
Tri-state Output : An oscillator with this feature allows the output to be placed a high impedance state. This feature is activated by application of a logic control voltage to pin 1 of the oscillator.
Start-up Time : That means the specified time from oscillator power-up to the time the oscillator reaches steady state oscillation. SOOJUNG clock oscillators presents a start-up time of less than 10 ms at Vcc-4.75 V for a 5V power supply.
Output enable time : The output enable time refers to the time before oscillation output develops after a control signal is input with the oscillation output stopped for a model with output control function.
Output disable time : The output disable time refers to the time before oscillation output stops after a control signal is input in the oscillation output condition for a model with output control function.
● Compatible with 14-pin dual in line
● Drive TTL IC without analog design
● Quick start-up time
● Hermetically sealed metal case
● Case ground 14-pin / 8-pin for no radiation of electric wave
● Optionally available features: